The present disclosure relates to integrated circuits, and more specifically, to a resistor within a single diffusion break (SDB), an IC including the resistor and a related method.
Advanced manufacturing of ICs requires formation of individual circuit elements, e.g., transistors such as field-effect-transistors (FETs) and the like, based on specific circuit designs. A FET generally includes source, drain, and gate regions. The gate region is placed between the source and drain regions and controls the current through a channel region (often shaped as a semiconductor fin) between the source and drain regions. Gates may be composed of various metals and often include a work function metal which is chosen to create desired characteristics of the FET. Transistors may be formed over a substrate and may be electrically isolated with an insulating dielectric layer, e.g., inter-level dielectric (ILD) layer. Contacts may be formed to each of the source, drain, and gate regions through the dielectric layer in order to provide electrical connection between the transistors and other circuit elements that may be formed subsequent to the transistor in other metal levels. Resistors for an IC are oftentimes formed in ILD layers above the FETs. These layers are referred to as middle-of-line (MOL) layers and back-end-of-line (BEOL) layers. MOL layers are just above the front-end-of-line (FEOL) layers that include the FETs, and BEOL layers are above the MOL layers. Both MOL and BEOL layers provide scaling interconnects for the IC. Formation of the resistors in the MOL or BEOL layers requires a number of steps, e.g., masking, etching and depositing of materials, that adds to the complexity of the overall process and can reduce the yield window for these layers. The resistors also add thickness to the layers.
Fin-type field effect transistors (“FinFETs”) have become increasingly widespread because FinFETs offer better electrostatic control over the behavior in the channel than planar FETs. FinFETs are formed by creating a number of semiconductor fins on a substrate and placing a gate conductor perpendicularly across the fins. A FinFET is created by the gate forming a channel region below the gate in the fin, and source/drain regions formed in the fin aside the gate. A particular fin may be used to fabricate multiple devices by forming one or more diffusion breaks along the axial length of a fin, thus defining separate fin portions/devices by removing a portion of the fin and replacing it with a dielectric material. A diffusion break having a lateral width corresponding to the lateral width of one gate structure is referred to as a single diffusion break (SDB).